Integrated Circuit Expert Witnesses

integrated circuit expert testimony

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Integrated circuit expert witness candidates typically have advanced degrees, may be licensed professional engineers, and have extensive experience in semiconductor technology, semiconductor manufacturing, and/or electrical engineering. An integrated circuit expert witness must have a deep understanding not only of IC technology, but also of the semiconductor industry, market share and the developing technologies of the industry’s leading players.

Basic information on integrated circuit technology and semiconductor manufacturing is available through a chip market report from an industry analysis provider. But a semiconductor expert witness must have a deeper understanding of the market, its history, the progression of the technology and often an understanding of which competitors were working on various designs at different points of time during the initial development stage.

An expert witness in the integrated circuit field will typically provide his or her expertise in intellectual property matters, such as a patent litigation in the federal court. It could be a patent infringement case or trade secrets matter in the District Court, an Inter Partes Review (IPR) in the PTAB (where the only expert testimony is through a deposition), or a patent case or proceeding in the International Trade Commission (ITC). Less frequently, an electrical engineer might provide testimony in a torts matter like a product liability case involving the failure analysis of a consumer electronics or medical device.

While many integrated circuit consultants have forensic engineering expertise, the expert witness carries the additional responsibility of providing testimony before the court, in a manner whereby lay people (the judge and jurors) can understand the technical evidence.

A testifying expert, or expert witness, is generally the only one in the court who is allowed to provide testimony as to his or her opinion because it is an expert opinion. Regardless of whether this takes the form of testimony in a deposition or trial, or in expert reports, the engineering component will provide credibility to his or her analysis and allow the jury to consider the expert’s opinion with the weight it deserves. Cahn Litigation has completed numerous searches for an expert witness in the integrated circuit space, providing candidates for each case to the specifications provided by the attorney in charge.

Whether the case involves application specific integrated circuit (ASIC) technology, circuit simulation, semiconductor device manufacturing, analog integrated circuits, or IC design, Cahn Litigation Services has the experience required to turn an expert witness search around quickly and provide the right balance of expertise and testimony to support each unique project and its nuances.

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Integrated Circuit Expert Witness - Representative Bios

Please Note: All Cahn Litigation expert witness searches are customized to attorneys' precise specifications and preferences. Attorneys are encouraged to discuss search parameters with a Cahn search specialist.

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The below expert witness bios represent a small fraction of those Integrated Circuit experts known by Cahn Litigation Services. These bios are provided to give lawyers a sense of the Integrated Circuit landscape.

Expert Witness #244900

This expert has worked with PMOS, NMOS, and CMOS process technologies throughout this expert's career, including many years in the semiconductor industry. Following the stint in industry, this expert joined the Electrical Engineering Department at a University where this expert teaches graduate and undergraduate courses in semiconductor/integrated circuit design and test technology, electronic devices and circuits, and VLSI technology. At a major technology company, this expert contributed to a number of product technology programs including the 4K DRAM, CCDs, NMOS and CMOS process development and non-volatile memories (DIFMOS), one of the first commercial EEPROM devices. In addition, this expert is the inventor or co-inventor of fourteen patents in semiconductor memory circuits and related fields. A silicon device expert with specific emphasis on process, device design, device characteristics and the use of the devices within the integrated circuit memories, this expert's consulting activities include serving as an expert witness in the fields of integrated circuit and transistor technology, and in areas dealing with electrical and electronic product design and electrical safety. This expert has published a variety of technical papers on subjects ranging from floating-gate nonvolatile memories to digital converters to numerical analysis of storage times of DRAM cells incorporating ultrathin dielectrics. This expert holds thirteen patents in the field of semiconductor devices, processes and circuits, is an IEEE Senior Member and has extensive expert witness experience providing deposition and testimony in various courts for over one hundred cases.

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Expert Witness #123119

This expert holds B.S., M.S. and Ph. D. degrees in Electrical Engineering. This expert has worked on the design of bipolar differential amplifiers, as well as in the areas of custom IC design, software compatible gate array design, one- and two-dimensional device modeling, circuit modeling, and double level metal process development. This expert was Manager of a Signal Processing Design and Test Department, responsible for the design and test of high performance VLSI/VHSIC CMOS and BIMOS digital and analog ICs, the development of supporting design and test methodologies and CAD tools, functional and parametric test, and the development of high performance and high resolution DSP and oversampled systems.

This expert is a Distinguished Professor and Director of the High Performance VLSI/IC Design and Analysis Laboratory at a major university. This expert’s current research and teaching interests include:

On-Chip Interconnect, Power, and Substrate Coupling Noise

High Performance Digital and Analog Integrated Circuit Design

Three-Dimensional Integrated Design Methodologies, Algorithms, and Test Circuits

Circuits, Models, and Architectures Based on Emerging Technologies

Efficient Power Delivery for Highly Complex Integrated Systems

High Performance Clock Distribution Networks

This expert has authored twelve book chapters and many papers in the fields of high speed and low power CMOS design techniques, interconnect and substrate noise, pipelining and retiming, three-dimensional integration, and the theory and application of power and synchronous clock distribution networks. This expert has also authored or edited sixteen books. This expert is a Fellow of the IEEE, an editor of the Journal of Circuits, Systems and Computers, a Member of Analog Integrated Circuits and Signal Processing, Microelectronics Journal, Journal of Low Power Electronics, and Journal of VLSI Signal Processing, and a Member of the technical program committee of a number of conferences.

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Expert Witness #225861

This expert is an internationally recognized expert in the field of high-speed communication and computing, and the development of semiconductor devices. While primarily known for work in developing cellular communications, this expert founded and ran three semiconductor companies. This expert is intimately familiar with controlling and interfacing memories such as FLASH EEPROM, DRAM, and SRAM. In these companies, this expert designed and built many system-on-chip devices, which required memories to be embedded or externally interfaced with many different types of bus standards. This expert has designed and incorporated into chip designs, memory controllers, bus controllers, as well as the memory modules of various types and sizes. In addition, this expert has also designed memory cells (DRAM and FLASH EEPROM) as part of vertical floating memory structures to be embedded in the system-on-chip devices. This expert has developed and implemented a number of semiconductor integrated circuit chips. These integrated circuit chips include switch fabrics, processors, high speed interfaces, protocol transposers, controllers, and memory cells and arrays. This expert is an active member of IEEE. This expert has been an organizer for several international symposiums, a guest editor of international journals, and has given a number of invited talks. This expert holds several U.S. patents.

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Expert Witness #226413

This expert holds an MS and PhD in Electrical Engineering. This expert is a Licensed Professional Electronics Engineer and Expert Witness practicing forensic and technical electrical engineering consulting. This expert’s technical engineering practice includes the design, verification, measurement and testing of electronic signal processing hardware circuits and systems, both integrated circuits and electrical modules, which are used for communication and electro-mechanical control. This expert’s forensic engineering practice includes forensic investigation, advising, reporting and testimony in matters regarding intellectual property, patents, failure analysis, product liability, product requirements and specifications.

For many years this expert worked with built-in self-test (BIST) for integrated circuits. Both digital (which is most common) and analog. BIST systems which generate and deliver test stimulus to one or more circuit nodes, capture resulting signals at one or more circuit nodes, process the captured signals to derive an “answer” which is compared to an expected answer, and finally take action depending on the results.

This expert has extensive prior litigation experience, including hostile trial cross-examination and deposition questioning.

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Expert Witness #226812

This expert holds a Ph.D. in Electrical Engineering and has extensive experience developing Application Specific Integrated Circuits (ASIC), semiconductor memories (DRAM and variety of other types), and Programmable Logic (FPGA and PLD) products used in the design of digital computer and telecom systems. This expert has developed Electronic Design Automation (EDA) software products based on behavioral (C, Verilog and VHDL) synthesis and ASIC/FPGA placement-route (physical design). This expert created an engineering design methodology and directed a world-wide operation that released over 3000 gate array (ASIC) designs. This expert was a key contributor in development of various memory (DRAM, SRAM, & serial memory) and logic products. Several patents in semiconductor processing and device structures and ?C to RLT? software compiler technology was issued along with multiple Technical Disclosure Bulletins. This expert?s experience includes various types of re-configurable (Field Programmable Gate Array) logic hardware & software products.

This expert created an Application Specific Integrated Circuit (ASIC) design methodology many years ago that incorporated scan test FlipFlops on IO cells that can be used to test internal operations of ICs. This ASIC design methodology was used to create over 3,000 IC designs, a few of which employed the expensive ?scan-test? capability.

This expert?s numerous expert reports and depositions in IC-related patent litigation cases have resulted in favorable settlements, and this expert has testified in court on IC cases as well. This expert has acquired extensive prior art documents and products over years in the industry. This expert has also provided technical background at the patent office during Re-Examination reviews and at court tutorials.
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Expert Witness #248891

This expert holds a PhD and MS in Electrical Engineering, and presently serves as Professor of Electrical Engineering at a State University. For many years, this expert has taught a year-long sequence of graduate level classes in System-on-Chip design. Further, this expert's career has been spent as a professor doing research on VLSI design, both analog and digital, including SoC design. This expert has designed SoCs, fabricated them, and published the results. This expert's research interests center primarily on the design and computer-aided design of digital and analog integrated circuits. Ongoing projects include: optimal gate size and threshold voltage selection for absolute leakage and/or dynamic power minimization subject to a frequency constraint; fast, accurate simulation-based timing analysis; more accurate power estimation for digital circuits; ultra low power time-to-digital conversion; resilient logic and memory for truly sub-threshold operation; for example, highly reliable, very low area overhead asynchronous logic design operating at sub-threshold voltages. Also, the design of secure ICs that cannot be reverse engineered and reverse engineering PCBs that are damaged and/or discarded. This expert has extensive prior litigation experience including deposition and testimony.

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